IBM Nanostack architecture is revolutionizing artificial intelligence

IBM has developed a revolutionary new technology in the field of microelectronics, Zamin.uz reported.

The company introduced the Nanostack architecture, which allows placing 100 billion transistors on a crystal the size of a human fingernail. This breakthrough promises unprecedented performance and energy efficiency for artificial intelligence systems.

This news was reported by Ixbt.com. One of the key aspects of the new technology is that IBM refers to it as the world’s first chip in the sub-one-nanometer class.

The company has labeled its platform as the seven-angstrom node. One angstrom equals one-tenth of a nanometer, so seven angstroms is 0.7 nm.

This figure reflects the level of technological integration rather than the physical dimensions of the elements. The main advantage of the Nanostack architecture is its vertical layout.

According to the laws of modern physics, transistors cannot be indefinitely miniaturized due to effects such as observation and current leakage. IBM engineers solved this problem by stacking transistors not only side by side but also vertically, one on top of another.

Each basic element consists of two vertically connected transistors, each containing three nanosheet layers with a thickness of five nanometers—equivalent to about fifteen rows of silicon atoms.

Such density allows nearly doubling the number of elements compared to previous two-nanometer technologies. Energy efficiency and memory performance have also been significantly improved.

According to IBM’s estimates, transitioning to Nanostack technology could increase computational performance by 50% or reduce energy consumption by up to 70%. Additionally, SRAM memory density increases by 40%.

These metrics are critically important for data centers that consume vast amounts of electricity and for large-scale artificial intelligence models. Furthermore, IBM specialists announced at the IEEE symposium that they have achieved significant progress in scaling static random-access memory microsystems.

By arranging transistor channels in a specific order, they succeeded in reducing the height of memory cells by 40%, which opens the way to significantly increasing the size of processor cache memory.

Although this technology is currently demonstrated only in laboratory conditions and scientific forums, it is expected to serve as the foundation for future graphics and mobile processors.